搜索资源列表
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
AD574_1
- verilog实现的“状态机实现AD574数模转换”-verilog to achieve a " state machine to achieve AD574 digital-analog conversion"
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
ketflink_fsm
- VERILOG的按键去抖，采用状态机的实现方法-VERILOG shaking the keys to using a state machine implementation
softdrink_testbench
- 一种可应用于自动售货机的状态机的verilog HDL描述-Verilog HDL descr iption of a state machine used in vending machines
howwite_status_machine_with_Verilog
- 如何用verilog语言写好状态机的不错的文档，希望对大家有所帮助-How to use Verilog state machine language to write good documentation, I hope all of you to help
jiaotongdeng
- 这程序是利用状态机来控制交通灯verilog码-This procedure is the use of state machine to control the traffic lights verilog code
Heilbronn_Visit_Design
- 海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述-Heilbronn Visit Design Digital Combination Lock
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
seqdet
- Verilog编写的有限状态机的程序，实现对一二进制序列的检测，该有限状态机提供8个状态的，可以任意修改，作为测试。-Verilog written procedures for finite state machines to achieve the detection of a binary sequence, the finite state machine with 8 states, and can be freely modified, as a test.
EfficientSynthesizableFiniteStateMachineDesignusin
- 高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
StateMachine-based
- FPGA上的利用状态机实现的分频的verilog程序-verilog source code StateMachine-based for FPGA
div_res
- 这是一个用VERILOG实现的除法的指令，用状态机实现的，希望对大家有用-THIS IS A CODE FOR DIV OF VERILOG。ITS USEFUL...
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
FSM
- 这是用verilog硬件描述语言编的moore状态机代码-It is compiled verilog hardware descr iption language moore state machine code
floatmul
- 用verilog实现三十二位浮点数算法，通过状态机的方法实现。-32 floating-point implementation using verilog algorithm, the method adopted by the state machine implementation.
Advanced_Verilog_Design
- 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, b
example
- 我FPGA开发板的程序！！！包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了，主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..